DFT Implementation Lead

East Bay
December 19, 2024
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Job Description

Join the leading chiplet startup! As an Eliyan DFT Implementation lead, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will be responsible for crafting DFT implementation schemes for best-in-class PHYs and Controllers. You will work with a cross-functional team of experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products. We offer a fun work environment with excellent benefits. MUST BE WILLING TO WORK ONSITE – M-F

Key Responsibilities

  • Develop and implement innovative DFT IP and features to support ATE, in-system test, debug, and diagnostics.
  • Contribute to flow and methodology development working closely with the digital, analog and physical design teams
  • Collaborate with cross-functional teams to integrate DFT features into the RTL design and ensure seamless validation and verification.
  • Work closely with the STA methodology owner in defining hierarchical DFT constraints and multi-mode multi-corner sign-off
  • Produce area/power tradeoff against design choices made for improved DFT coverage
  • Own complete architecture, tool/vendor selection for DFT insertion, simulation, fault debug and characterization
  • Work closely with design, design-verification, and physical design teams to enable the integration and validation of test logic.
  • Participate in the development of innovative hardware DFT and physical design aspects for new silicon device models.
  • Create and maintain dashboards for tracking DFT collaterals to be handed over to Test Engineering, including coverage matrix
  • Responsible to produce a DFT architecture document for every PHY / chiplet programs specifying a detailed list of collaterals for customers
  • Work closely with physical implementation teams to define the optimal MMMC corners for various stages of implementation vis-à-vis placement, CTS and routing for DFT modes.

Qualifications

  • Bachelor’s or Master’s degree in Electrical or Computer Engineering.
  • At least 15 years of experience in hardware DFT, testability, and physical design.
  • Proven expertise in JTAG protocols, scan and BIST architectures, memory BIST, and boundary scan.
  • Experience with ATPG and EDA tools (Tessent, TetraMax, Genus, Tempus, DC, PrimeTime)
  • Experience with gate-level simulation, running SDF annotated simulations for test vector set
  • Experience with post-silicon validation and debug, ATE patterns bring-up on Advantest ATEs.
  • Scripting skills in Tcl, Python, or Perl.
  • Proven track record of being a highly visible contributor as part of a start-up like environment
  • Problem solver and efficient in written/verbal communication – excellent data organization skills and churns high quality work product
  • Ability to work cross-functionally with digital, analog design, and implementation teams